The present application relates generally to an improved data processing apparatus and method and more specifically to an apparatus and method for a multithreaded programmable direct memory access engine.
The Cell Broadband Engine (CBE), a multi-core processor architecture available from International Business Machines, Inc., describes a memory flow controller (MFC) that is specific to each synergistic processing unit (SPU). The main purpose of this memory flow controller is to maintain and process queues of direct memory access (DMA) commands from the MFC's associated SPU or from a power processor element (PPE) or other devices. The MFC's DMA engine executes the DMA commands. This allows the SPU to continue execution in parallel with the MFC's DMA transfers.
This enables software on the PPE or other SPUs to access the MFC resources and control the SPU. Privileged software on the PPE or other SPUs also provides address-translation information to the MFC for use in DMA transfers. DMA transfers are coherent with respect to system storage. Attributes of system storage (address translation and protection) are governed by the page and segment tables of the PowerPC® architecture.
The MFC supports channels and associated Memory Mapped Input/Output (MMIO) registers for the purposes of enqueueing and monitoring DMA commands, monitoring SPU events, performing interprocessor-communication via mailboxes and signal-notification, accessing auxiliary resources such as the decrementer (timer), and other functions. In addition to supporting DMA transfers, channels, and MMIO registers, the MFC also supports bus-bandwidth reservation features and synchronizes operations between the SPU and other processing units in the system.
However, current DMA engines require too much supervision from software running on the host processor, either the PPE or the SPUs, limiting the host processor performance and the total latency of accessing needed data from complex data structures.